A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a ferroelectric capacitor and its manufacture method.
B) Description of the Related Art
Recent multiple function semiconductor devices have a strong need of mixedly fabricating a logic circuit and a memory. A logic circuit is often constituted of a CMOS circuit. Many manufacture processes for a CMOS circuit have already been established. A ferroelectric memory is not widely used which is a non-volatile memory whose contents are retained even if a power supply is cut off. There are many manufacture processes for a ferroelectric memory still not established. It is desired that the CMOS manufacture processes should not interfere with the ferroelectric capacitor manufacture processes.
Japanese Patent Laid-open Publication No. HEI-10-261767 discloses the manufacture process of: forming a MOS transistor in an active region defined by an element isolation field oxide film; forming an oxidation-duravble silicide layer; covering the MOS transistor with a silicon oxide layer; thereafter forming a Ti/Pt lower electrode, a PZT ferroelectric layer and a Pt upper electrode on the element isolation region in a tiered stand (stepped lamination) shape; covering the substrate with an interlayer insulating film; forming contact holes through the interlayer insulating film, the contact holes reaching the upper electrode, lower electrode and source/drain regions; and forming Ti/TiN/Al wirings.
Japanese Patent Laid-open Publication No. HEI-11-195768 discloses the manufacture method of forming a ferroelectric capacitor having a Pt/SRO lower electrode, a PZT ferroelectric layer and an SRO/Pt upper electrode, in which the SRO layer of the lower electrode is formed in an amorphous phase in a reduced pressure atmosphere and thereafter the SRO layer is subjected to heat treatment in an oxidizing atmosphere to crystallize it.
Japanese Patent Laid-open Publication No. 2003-258201 discloses the manufacture method of: burying (or embedding) a tungsten plug in an interlayer insulating film; forming an oxygen barrier conductive layer of Ir, TiN, TiAlN or the like on the interlayer insulating film; forming on the oxygen barrier conductive layer a lower electrode layer of a single layer or a lamination layer of an Ir layer, a Pt layer, an IrO layer, an SRO layer or the like; forming an oxide perovskite ferroelectric layer such as PZT, SBT, and BLT; forming on the oxide perovskite ferroelectric layer an upper electrode layer of a single layer or a lamination layer of a Pt layer, an Ir layer, an IrO layer, an SRO layer, a PtO layer or the like; forming a first hard mask layer of a TiN layer, a TaN layer, a TiAlN layer or the like and a second hard mask layer of silicon oxide; patterning the ferroelectric capacitor structure; covering the ferroelectric capacitor structure with an encapsulation film having a hydrogen shielding capability such as a TiO2 layer and an Al2O3 layer, and an interlayer insulating layer of silicon oxide; forming a via hole reaching the upper electrode; and burying a tungsten plug in the via hole.
Japanese Patent Laid-open Publication No. 2003-152165 discloses the manufacture process of: forming a ferroelectric capacitor of a tiered stand shape above an element isolation region; covering the ferroelectric capacitor with an interlayer insulating film; forming contact holes through the interlayer insulating film to expose an upper electrode, a lower electrode and source/drain regions, burying a TiN hydrogen barrier layer and a W film in the contact holes to form conductive plugs, and forming aluminum wirings on the conductive plugs.